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1–6
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MAINTENANCE reads and writes
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
The hardware tests also cover the following control symbol types:
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Status
Packet-accepted
Packet-retry
Packet-not-accepted
Start-of-packet
End-of-packet
Link-request, Link-response
Stomp
Restart-from-retry
Multicast-event
Interoperability Testing
Altera performs interoperability tests on the RapidIO IP core, which certify that the
RapidIO IP core is compatible with third-party RapidIO devices.
Altera performs interoperability testing with processors and switches from various
manufacturers including:
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Texas Instruments Incorporated
Integrated Device Technology, Inc. (IDT)
Testing of additional devices is an on-going process.
In addition, the RapidIO IP core v9.0 successfully passed RIOLAB’s Device
Interoperability Level-3 (DIL-3) testing in 2009.
Performance and Resource Utilization
This section contains tables showing IP core variation size and performance examples.
Appendix D, Calculating Resource Utilization for Modular Configurations outlines
ways you can reduce resource utilization to create smaller IP core variations.
Table 1–3 to Table 1–6 list the resources and expected performance for selected
variations that use these modules:
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Physical layer with 8 KByte transmit buffers and 4 KByte receive buffers
Transport layer
Input/Output Avalon-MM master and slave
The numbers of LEs, combinational ALUTs, ALMs, and primary logic registers are
rounded up to the nearest 100.
Table 1–3 shows results obtained using the Quartus II software v13.0 for the following
devices:
RapidIO MegaCore Function
User Guide
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Arria V GX (5AGXBB1D4F31C4)
May 2013 Altera Corporation
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